The present invention relates to the field of integrated circuits, and more specifically to the manufacturing of an inductance formed above a semiconductor substrate.
FIGS. 1A and 1B show, respectively in a top view and in a cross-section view along line B-Bxe2x80x2 of FIG. 1A, a conventional example of an inductance 1 formed above a semiconductor substrate 2. Inductance 1 includes a number of generally concentric turns or spirals (at least one spiral) obtained by the deposition of a conductive element on an insulating layer 3 (FIG. 1B). Insulating layer 3, for example, silicon oxide, rests on the last metallization level 4 added on substrate 2 after forming of integrated components in this substrate. In the example of FIG. 1B, two other metallization levels 5, 6 have been illustrated in dotted lines between substrate 2 and upper level 4. Each level is of course separated from the underlying level by an insulating layer, respectively 7, 8. The conductive element of inductance 1 is conventionally of constant width and thickness. It is deposited on insulating layer 3, in the form of a flat winding from a first internal end 10 to a second external end 11.
To enable connection of inductance 1 to the rest of the integrated circuit or to a terminal of a package, it is necessary to provide a contact recovery from internal end 10 of the winding to the outside of this winding. Conventionally, this contact recovery is obtained by using an underlying metallization level (generally, upper level 4). A conductive track 12 (generally rectilinear) is formed therein between the location under internal end 10 of inductance 1 and the location under a pad 13 outside of the winding. Pad 13 is formed on insulating layer 3 in the same conductive material as the winding of inductance 1. Vias 14 and 15 (for example, made of tungsten) electrically connect end 10 and pad 13 to the respective ends of underlying track 12.
In the forming of an inductance, its quality factor is generally desired to be optimized. Among the parameters having an influence upon this quality factor, the parasitic resistance (series resistance) is a major parameter. To reduce the resistance of the conductive element against the flowing of current, its section is generally desired to be maximized. Not only the thickness, but also the width of the spirals of inductance 1 are then increased.
A disadvantage is that the contact recovery from the internal end of the winding introduces a series resistance that annuls the beneficial effects of the section increase of this winding. Indeed, the thickness of the metal levels underlying the winding is imposed by the technology in which the other components integrated with the inductance are manufactured.
For example, the metallization levels are formed in aluminum deposited over a thickness from 0.8 to 1 xcexcm. The conductive level added on top of the structure and in which the spirals are formed has, in the case of aluminum, a thickness on the order of 2.5 xcexcm. However, to avoid adversely affecting the integrated circuit manufacturing, such a thickness increase is only conceivable on the last deposited level.
This problem is posed whatever the number of spirals of the inductance and whatever the conductive materials used. Further, it is more generally encountered each time a crossing is desired to be made in a winding of an integrated inductance.
The present invention aims at providing a novel integrated circuit inductance that overcomes the disadvantages of known inductances.
The present invention more specifically aims at solving the problems associated with the contact recovery from the internal end of the inductance.
More generally, the present invention aims at providing a solution to the problem of crossing, by contact recovery in a lower level, of a flat winding of an inductance.
To achieve these objects, the present invention provides an integrated inductance, formed of a flat winding of at least one spiral made of a semiconductor material above a substrate provided with at least one underlying conductive level, in which the winding is crossed at least once by a contact recovery track, the spiral width being reduced above said contact recovery track.
The present invention also provides an integrated inductance, formed of a winding of several spirals, the width of at least one spiral and/or of at least one interval separating two spirals being reduced above said contact recovery track.
According to an embodiment of the present invention, the crossing is used for the contact recovery from an internal end of the winding to an external pad.
According to an embodiment of the present invention, the pattern of the spirals is such that the external spiral is, at the level of the contact recovery, closer to the center of the winding than the rest of this external spiral.
According to an embodiment of the present invention, the resistance per square of the conductive material constitutive of the winding is substantially smaller than the resistance per square of the underlying conductive level in which is formed the contact recovery, the thickness of the conductive material constitutive of the winding being, preferably, substantially greater than the thickness of the underlying conductive level.
According to an embodiment of the present invention, the intervals, in the contact recovery alignment, between the two connected winding portions, are minimized.
According to an embodiment of the present invention, the length of the narrowed section(s), which depends on the width of the contact recovery track, is chosen to be as short as possible.
According to an embodiment of the present invention, the conductive material is aluminum, the underlying conductive level being also made of aluminum.
According to an embodiment of the present invention, said conductive material is copper having a thickness of several tens of micrometers, the underlying conductive level being made of aluminum of a thickness on the order of one micrometer.
According to an embodiment of the present invention, said conductive level is formed by the upper metallization level used for the interconnections of other components of the integrated circuit.